Airborne Ethernet Switch

The Airborne Ethernet Switch (AES) is a CPU managed Ethernet switch with support for Quality of Service (QoS), 802.1Q, and RMON counters. It contains 24 10BASE-T/100BASE-TX transceivers (PHYs), and 2 SERDES interfaces that are used as 10/100/1000BASE-TX interface to implement a Sniffer port and optional fiber 100BASE-FX port. The switch contains a non-blocking four traffic class QoS switch fabric, a high-performance address lookup engine, and a 3 Mbit frame buffer memory.

The shared memory-based QoS switch fabric architecture provides non-blocking switching performance in all traffic environments. Packets are directed into one of four traffic class queues based upon Port, IEEE 802.1p tagged frames, Ipv4's Type of Service (TOS) or Differentiated Services (DS), Ipv6's Traffic Class, 802.1Q VID, Destination MAC address or Source MAC address.

The AES supports zero packet loss under temporary traffic congestion implementing different flow control schemes.

24 Ports, 10/100 BaseT Ethernet
Sniffer Port
Optional Fiber Port
Error Monitoring and Error Recovery
Compliant with IEEE 802.3, 802.3u and 802.3x
Includes Built In Test
Meets Mil-Std-810 environmental requirements
Mil-Std-704A compatible 28 VDC Power Supply

Overview

The Airborne Ethernet Switch (AES) constitutes a part of the avionics system of both military and commercial aircraft. It serves as the backbone of advanced communication between the various components of the avionics in modern aircraft.

System quality

The AES PHY Virtual Cable Tester feature uses Time Domain Reflectometry (TDR) to determine the quality of the cables, connectors, and terminations. Some of the possible problems that can be diagnosed include opens, shorts, cable impedance mismatches, bad connectors, termination mismatches, and bad magnetics.

Fiber Optic Link

For the fiber optic interface port 100BASE-FX far end fault indication provides a mechanism for transferring information from the local station to the link partner that a remote fault has occurred (FEFI idle pattern).

System Management

The managing CPU performs all the initializing activities, BIT functions including RMON counters per port management. The CPU is connected to the switch and to the GBIT PHY via standard management serial interface compliant with IEEE 802.3u clause 22. The CPU has access to all switch port registers providing it with a full control of the switch QoS capabilities. The CPU under software control (user dynamically defined) will add/remove monitoring ports to the sniffer switch port thus providing monitoring capabilities for all the switch ports or just for predetermined groups. The CPU contains MII compatible MAC connected to the switch fabric providing external access to diagnostic and management activities from every switch port.